The present invention relates to a semiconductor memory, especially a DRAM (Dynamic Random Access Memory) and, more particularly, to a circuit architecture suitable for reducing the operating time of the so-called "clear mode" by writing predetermined data in all memory cells which erase the data of all memory cells. Thus, by "clear mode" is meant a data change in all memory cells in an array.
In recent years, the DRAM has had its applications extended to graphics systems. The memory for this application frequently accomplishes the so-called "clear mode". In the memory of the prior art, however, the write and read of the data are accomplished bit by bit. At present, the DRAM of this type is a mainstream. In case the clear mode operation is requested, such memory is required sequentially to write predetermined data at each bit so that the clear mode operation takes a long time. In the case of the DRAM of 1 Mbits, for example, the time for the clear mode operation is about 0.2 seconds if the cycle time is 200 nanoseconds. Thus, the time for the clear mode operation has been a problem with prior art memory. The art relating to the device of this kind is disclosed in IEEE Journal Solid-State Circuits, Vol. SC-19, No. 5 (1984), pp. 619 to 623, for example.